A common approach to fault tolerant system designs involves employing redundant or spare logic units. In one such approach, the system is designed to include five identical logic units which operate in parallel, and the respective outputs of the units are polled to determine correct output data. Specifically, if the results of the poll reveal that at least three of the five units output identical data, then such identical data is assumed correct. While this approach will provide relatively accurate output data, the approach is disadvantageous since it requires employing five separate units each of which is designed to output the same data.
In another approach, the fault tolerant system employs only two units which operate in parallel. In this system, the respective outputs of the two units are compared, and if they do not match, then a known signature is employed through both systems in an attempt to determine the correct and faulty outputs. This system is also disadvantageous in that several cycles must be performed when the unit outputs do not match, thereby decreasing the operating speed of the system.
The following references are examples of fault detection logic systems.
IBM Technical Disclosure Bulletin, Vol. 27, No. 10B, pages 6148-6152, March 1985, discloses a Differential Cascode Voltage Switch (DCVS) circuit in which outputs of DCVS circuit trees are tested for faults.
U.S. Pat. No. 4,638,482 discloses a system for testing a differential logic network. The system includes both a differential exclusive OR gate having several inputs for receiving complementary signals from a differential logic network, and also a conventional exclusive OR gate, coupled to receive the outputs of the differential exclusive OR gate, for detecting the presence of a fault or error in the differential logic network.
U.S. Pat. No. 4,739,498 discloses a system including both an error detector circuit for detecting a fault in a device, and also a switching arrangement for switching from the detected defective device to a redundant duplicate device.
U.S. Pat. No. 4,358,823 discloses a double redundant processor system including first and second master processors for processing data. When one of the first and second master processors is active, the other processor is in a standby mode. The system further includes an alarm monitor which in response to an error signal, deactivates the active master processor and activates the standby master processor.
U.S. Pat. No. 4,727,313 discloses a method of simulating a DCVS circuit. In the method, various faults are simulated by holding selected internal signals of the circuit at faulty values.
U.S. Pat. No. 4,719,629 discloses an error correction circuit including redundant logic NOR circuits.
U.S. Pat. No. 4,570,084 discloses a differential logic circuit.
U.S. Pat. Nos. 4,709,166; 4,686,392 and 4,656,417 disclose further examples of cascode logic circuits.